The present invention relates to integrated circuit structures and, more particularly, to dielectric isolation in integrated circuit structures.
The form of most existing integrated circuits is the so-called monolithic form. Such a structure contains great numbers of active and passive devices in a block or monolith of semiconductor material. Electrical connections between these active and passive devices are generally made on a surface of the semiconductor block of material. Until the present, junction isolation has been by far the most widely practiced manner of isolating devices or circuits in the integrated circuit from each other. For example, active P type diffusions are customarily used to isolate conventional and P-N bipolar devices from one another and from other devices such as the resistors and capacitors. Such junction isolation is also used in integrated circuits utilizing field effect transistor devices. More detailed descriptions of junction isolation may be found in U.S. Pat. Nos. 3,319,311; 3,451,866; 3,508,209 and 3,539,876.
Although junction isolation has provided excellent electrical isolation in integrated circuits which have functioned very effectively over the years, at the present stage of the development of the integrated circuit art, there is an increasing demand in the field of digital integrated circuits for faster switching circuits. It has long been recognized that the capacitive effect of the isolating P-N junctions has a slowing effect on the switching speed of the integrated circuits. Up to now, the switching demands of the integrated circuits have been of a sufficiently low frequency that the capacitive effect in junction isolation has presented no major problems. However, with the higher frequency switching demand which can be expected in the field in the future, the capacitive effect produced by junction isolation may be an increasing problem. In addition, junction isolation requires relatively large spacing between devices, and, thus, relatively low device densities which is contrary to higher device densities required in large scale integration. Junction isolation also tends to give rise to parasitic transistor effects between the isolation region and its two abutting regions. Consequently, in recent years there has been a revival of interest in integrated circuits having dielectric isolation instead of junction isolation. In such dielectrically isolated circuits, the semiconductor devices are isolated from each other by insulative dielectric materials.
Conventionally, such dielectric isolation in integrated circuits has been formed by etching channels in a semiconductor member corresponding to the isolation regions. This leaves an irregular or channeled surface over which a substrate, usually a composite of a thin dielectric layer forming the interface with the semiconductor member covered by a thicker layer of polycrystalline silicon is deposited. Then the other surface of the semiconductor member is either mechanically ground down or chemically etched until the bottom portions of the previously etched channels are reached. This leaves the structure wherein a plurality of pockets of semiconductor material surrounded by the dielectric layer are supported on the polycrystalline silicon substrate and separated from each other by extensions or fingers of the polycrystalline substrate. Such structures have been described in the prior art in patents such as U.S. Pat. Nos. 3,391,023; 3,332,137; 3,419,956; 3,372,063; 3,575,740; 3,421,205; 3,423,258; 3,423,255 and 3,478,418.
Complete dielectric isolation, as set forth in the prior art presented by the referenced patents, has had several shortcomings which have prevented it from being fully successful in high speed circuitry where it was particularly needed. Such high speed circuitry requires particularly shallow devices. Thus, the semiconductor pockets were required to be in the order of 0.1 mil in thickness. However, because of wafer handling requirements in semiconductor integrated circuit fabrication techniques, the substrates which had to be etched or ground down were in the order of 6 to 8 mils in thickness. In practicing this prior art, fabricators experienced considerable difficulty in grinding, lapping or etching from 6 to 8 mils of material through a substrate with no inaccuracies which would affect the 0.1 mil pockets.
In addition, the interface between the original semiconductor member and the dielectric polycrystalline composite deposited on such member was, in effect, "corrugated" in cross-section due to the channels which were etched in said semiconductor member. Because of this "corrugated" interface, the opposite surface of the polycrystalline substrate being deposited was also "corrugated". We believe that such corrugations in the bottom surface of the substrate would subject the wafer to unnecessary stresses when pressure was being applied to the integrated circuit wafer or chip during fabrication steps such as thermocompression bonding or when applying probes to the wafer during testing. Such stresses could result in structural defects in the integrated circuit. Also, during wafer processing where it is customary to support the wafer on a heat sink for heat dissipation from the wafer, the corrugated bottom surface of the wafer would reduce the heat transfer to the sink.
In addition, because of the "corrugated" interface, there is no practical manner in which wiring between pockets of semiconductor material could be accomplished utilizing "buried" conductive connectors, e.g., metallic connectors at said interface.
Further, because the fingers of polycrystalline semiconductor material extend into the dielectric isolation between the semiconductor pockets, such prior art dielectrically isolated corrugated structures are still subject to lateral parasitic capacitances between the semiconductor pockets and the fingers of semiconductor material from the supporting substrate.
Recent work in the art appears to have gone a long way in the solution of the problem of removal of the major portion of the semiconductor member to leave the semiconductor pockets. In accordance with the publication "Application of Preferential Electrochemical Etching of Silicon to Semiconductor Device Technology", M. Theunissen et al., Journal of the Electrochemical Society, July 1970, pp. 959 to 965, selective anodic electrochemical etching may be used to remove and, thereby, cleanly and accurately separate the major portion of the semiconductor member from the semiconductor pockets in which the devices are to be formed. The publication, and particularly with reference to FIG. 8 thereof, sets forth that by utilizing a semiconductor member having a relatively thick, highly doped substrate and a thinner, lightly doped epitaxial layer in which the grooves are etched prior to the deposition of the dielectric polycrystalline silicon supporting substrate, the highly doped portion of the semiconductor material can be removed by the anodic electrochemical etching technique described to leave the lightly doped pockets of semiconductor material. However, this structure still has the previously described "corrugated" interface as welll as the consequential "corrugated" bottom surface on the polycrystalline silicon supporting substrate.